‹Programming› 2020
Mon 23 - Thu 26 March 2020 Porto, Portugal
Tue 24 Mar 2020 16:00 - 16:30 at W1 - Dynamic Runtime Optimizations

Since the early conception of managed runtime systems with tiered JIT compilation, several research attempts have been made to accelerate the bytecode execution. In this paper, we extend prior attempts by performing an initial analysis of whether heterogeneous hardware accelerators in the form of Graphics Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAS) can help towards achieving higher performance during the bytecode interpreter mode. To answer this question, we implemented a simple parallel Java bytecode interpreter written in OpenCL and executed it across a plethora of devices, including GPUs and FPGAs. Our preliminary evaluation shows that under specific workloads, hardware acceleration can yield up to 17x better performance compared to traditional optimized interpreters running on Intel CPUs and up to 214x compared to ARM CPUs.

Tue 24 Mar
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16:00 - 17:30: Dynamic Runtime OptimizationsMoreVMs at W1
16:00 - 16:30
Talk
MoreVMs
Juan FumeroUniversity of Manchester, UK, Athanasios StratikopoulosThe University of Manchester, Christos KotselidisKTM Innovation / The University of Manchester
Pre-print
16:30 - 17:00
Talk
MoreVMs
Johannes HenningHasso Plattner Institute, Tim FelgentreffOracle Labs, Potsdam, Fabio NiephausHasso Plattner Institute, University of Potsdam, Robert HirschfeldHasso-Plattner-Institut (HPI), Germany
17:00 - 17:30
Talk
MoreVMs
Filippo SchiavioUniversità della Svizzera italiana, Daniele BonettaOracle Labs, Walter BinderUniversity of Lugano, Switzerland